Cache valid identification mechanisms in existing cache designs occupy a large amount of area and consume considerable static and dynamic power. The space and power problems are worse for configurable cache designs involving tradeoffs between a number of sets in the design and line lengths. The configurability is desired when using the same device for different software applications having difference locality characteristics.
The cache valid identification mechanisms identify which of the data words stored in the cache are valid and which contain uninitialized or invalid data. A common way to mark validity is by allocating a valid bit for every data word stored in the cache memory. The implementation of the valid bit is usually accomplished with (i) registers which are easy to access and enable fast access or (ii) a memory where allowed by access time constraints.
Referring to FIG. 1, a diagram of a conventional cache valid identification mechanism 20 under a static condition is shown. An example cache line 22 contains several locations 24a-24x, each location storing a data word. A multi-bit register 26 is allocated to the cache line 22. The register 26 contains multiple bits 28a-28x, a single bit for each of the locations 24a-24x. Arrows illustrate links between the register bits 28a-28x and the corresponding locations 24a-24x. 
The register 26 reflects the validity state of the cache line 22. The data words in the locations 24a-24x that correspond to set bits (i.e., logical one bits) 28a-28x are valid. The data words in the locations 24a-24x that correspond to reset bits (e.g., logical zero bits) 28a-28x are invalid. When data is fetched from a main memory to a cache line 22, the fetched data may fill only a portion of the cache line 22. As a result, some of the locations (i.e., 24a-24j) contain stale data words and are marked as invalid. The fetched data words are stored in the cache line 22 from a starting address (i.e., location 24k) to the end of the cache line (i.e., location 24x). The fetched data words are marked as valid.
Referring to FIG. 2, a diagram of the conventional cache valid identification mechanism 30 under a fetch condition is shown. While a fetch burst is in progress, the bits 28a-28x corresponding to the new data words already copied into the cache line 22 (i.e., locations 24k-24m) are set to valid. The locations of the data words yet to be fetched (i.e., locations 24n-24x) are marked as invalid until the new data words have been stored in the cache line 22. As each new data word is written into a location 24a-24x during the burst, the corresponding bit 28a-28x is set to indicate valid. Upon reset, or when a word is flushed out of the cache memory, the corresponding valid bits 28a-28x are reset.
Referring to FIG. 3, a block diagram of a portion of a conventional cache 40 is shown. The cache 40 has a group of comparators 42 that compare a high portion of an address with tags stored in a tag array 44. Upon a cache hit, the comparators 42 identify a particular register (i.e., register 26) associated with the cache hit from among a group of registers 46. A multiplexer 48 uses a lower portion of the address to route a particular register bit to indicate a valid/not valid location.